An ESD (Electro-Static Discharge) protection circuit is an important component part of a display device, and can ensure the display device from electrostatic damage in producing, transporting, and operating procedures. FIG. 1 shows a schematic diagram of a structure of an array inside the display device and an ESD protection circuit surrounding the array in the prior art. Referring to FIG. 1, in normal operation, there is only a small leakage current flowing from a data (Vdata) line 11 or a gate (Vgate) line 12 to a gate high level (VGH) line 14 and a gate low level (VGL) line 15; when ESD occurs, positive charges of the Vdata line 11 or the Vgate line 12 may be released quickly to the VGH line 14 through the ESD protection circuit 13 and negative charges of the Vdata line 11 or the Vgate line 12 may be released quickly to the VGL line 15 through the ESD protection circuit 13, wherein levels of the VGH line 14 and the VGL line 15 are a high level and a low level of a gate scanning signal, respectively.
FIG. 2 shows a schematic diagram of a structure of an ESD protection circuit in the prior art. As shown in FIG. 2, the ESD protection circuit 13 as shown in FIG. 1 comprises two enhanced P-type thin-film transistors (TFTs) M1 and M2, descriptions will be given by taking the Vdata line 11 as an example. A thin-film transistor M1 has a gate connected to the Vdata line 11, a source connected to the Vdata line 11, and a drain connected to the VGH line 14; and a thin-film transistor M2 has a gate connected to the VGL line 15, a source connected to the VGL line 15, and a drain connected to the Vdata line 11. In normal operation. At this time, a level of the Vdata line 11 is between the level of the VGH line 14 and the level of the VGL line 15, there is no forward current being released from the Vdata line 11 to the VGH line 14 and the VGL line 15, and there is only a very weak reverse leakage current being released to the VGH line 14 and the VGL line 15. When ESD occurs, if positive charges are accumulated on the Vdata line 11, the level of the Vdata line 11 is higher than the level of the VGH line 14, and the thin-film transistor M1 is conductive reversely to release the positive charges on the Vdata line 11 to the VGH line 14; if negative charges are accumulated on the Vdata line 11, the level of the Vdata line 11 is lower than the level of the VGL line 15, the thin-film transistor M2 is conductive reversely to release the negative charges on the Vdata line 11 to the VGL line 15 to ensure the array inside the display device from the electrostatic damage.
At present, the oxide thin-film transistor has advantageous of high mobility, good uniformity and low cost, and thus has a rapid development. However, the existing production process has determined that an oxide thin-film transistor can only be a depletion mode thin-film transistor. If the depletion mode thin-film transistor is applied to the ESD protection circuit shown in FIG. 2, it will result in that large amounts of current will be released, in a normal operation, from the Vdata line 11 to the VGH line 14 and the VGL line 15, which may cause the array inside the display device cannot operate normally and even may damage an external driving circuit.